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INTEGRATED CIRCUITS
DATA SHEET
SZA1000 QIC digital equalizer
Product specification File under Integrated Circuits, IC01 1998 Feb 16
Philips Semiconductors
Product specification
QIC digital equalizer
FEATURES * 3-wire serial interface for programming and status reading * Suitable for MFM (Modified Frequency Modulation), RLL 1,7 (Run Length Limited) and similar codes * Transfer rates with MFM code from 250 kbits/s to 4 Mbits/s * Transfer rates with RLL(1,7) code from 500 kbits/s to 12 Mbits/s * Programmable FIR (Finite Impulse-Response) filter makes it possible to equalize complex and asymmetric channel impulse responses * Programmable fixed and tracking qualification thresholds provide reliable data recovery in read mode, and reliable bad sector detection in verify mode * Read pulse output for floppy tape drives * Digital data synchronizer based on digital PLL with maximum likelihood detector for a better error rate than can be achieved with conventional analog circuits * Data verification can be used (with the maximum likelihood detector switched off) to find bad sectors on drives with conventional read electronics * Servo stripe detection for TR4, QIC3080 and similar formats * Gap detector * 2 programmable current sources QUICK REFERENCE DATA SYMBOL VDDD1; VDDD2 VDDA1; VDDA2 IDDD1; IDDD2 IDDA1; IDDA2 fclk(CLKIN) fclk(WEQCLK) Tamb PARAMETER digital supply voltage analog supply voltage digital supply current analog supply current read circuit clock frequency WEQ circuit clock frequency ambient operating temperature fs = 24 MHz CONDITIONS MIN. 4.5 4.5 - - - - 0 TYP. 5.0 5.0 32 50 24 24 -
SZA1000
* Peak-to-peak amplitude detector with lowpass filter for servo burst reading * Fully digital PLL for clock and data recovery: - Fully programmable behaviour - No external components, no tolerance problems - Programmable window shift - Fast run-in capability - Ideal zero phase restart. * Parallel 8-bit input and output for product development and production testing * Programmable WEQ (write equalization) circuit with transfer rates of up to 2 Mbits/s for floppy tape drives and up to 8 Mbits/s for drives with internal controllers. GENERAL DESCRIPTION The SZA1000 is a single chip digital equalizer for single channel QIC (Quarter Inch Cartridge) systems with MR (Magneto Resistive) heads. It can be used with QIC 3010, QIC 3020, QIC 3080, QIC 3095, Travan 2, 3, 4 and 5, and similar formats. It replaces a pulse detector, programmable filter and data synchronizer, and adds a FIR filter to the conventional analog solution. This makes it possible to equalize yoke-type MR heads as well as SIG (Sensor In Gap) MR heads.
MAX. 5.5 5.5 - - 24 36 70
UNIT V V mA mA MHz MHz C
ORDERING INFORMATION TYPE NUMBER SZA1000H PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm) body 10 x 10 x 1.75 mm VERSION SOT307-2
1998 Feb 16
2
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1998 Feb 16
Vref INA INB RESET TEST AUXBUS0/WDOUT AUXBUS1 to AUXBUS7 11 to 18 8 I/O MUX LPF 15 kHz 37 32 33 30 31 ADC HPF LPF R
BLOCK DIAGRAM
Philips Semiconductors
QIC digital equalizer
PACLK 29 7 FIR INTERPOL R CLK DIV XOSC/ CLK IN 6 CLKOUT CLKIN RG LTD
SZA1000
20 19
PLL
MAXIMUM LIKELIHOOD DETECTOR 27
SRD/RD
WDIN WGATE WEQCLK WEQEN WGX SDEN SCLK SDIO
10 4 9 3 36 23 24 22 SERIAL INTERFACE IDAC DIFF 8, 28, 34, 41 4 Rref IO1 IO2 VSSD1 VSSD2 VSSA1 VSSA2 5, 26, 35, 42 4 VDDD1 VDDD2 VDDA1 VDDA2 DAC WRITE EQUALIZATION AMPL. DETECTOR
AMPL. QUALIFIER + GAP DETECTOR
3
STRIPE DETECTOR
MUX
25
RRC
21
GAP/STRIPE
LPF 8 MHz
READ PULSE
38 1
2
39 44 40 43
MGG582
EYEA EYEB
CMPB CMPA
Product specification
SZA1000
Fig.1 Block diagram.
Philips Semiconductors
Product specification
QIC digital equalizer
PINNING SYMBOL IO1 IO2 WEQEN WGATE VDDD1 CLKIN CLKOUT VSSD1 WEQCLK WDIN AUXBUS0/WDOUT AUXBUS1 AUXBUS2 AUXBUS3 AUXBUS4 AUXBUS5 AUXBUS6 AUXBUS7 LTD RG GAP/STRIPE SDIO SDEN SCLK RRC VDDD2 SRD/RD VSSD2 PACLK RESET TEST INA INB VSSA1 VDDA1 WGX Vref Rref EYEA CMPA 1998 Feb 16 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 programmable current source programmable current source write equalization circuit enable input write gate input; active LOW digital supply voltage external clock or crystal oscillator input crystal oscillator output digital ground write equalization circuit clock input write equalization circuit data input DESCRIPTION
SZA1000
bit 0 auxiliary I/O bus or write equalization output to write amplifier bit 1 auxiliary I/O bus bit 2 auxiliary I/O bus bit 3 auxiliary I/O bus bit 4 auxiliary I/O bus bit 5 auxiliary I/O bus bit 6 auxiliary I/O bus bit 7 auxiliary I/O bus fast lock to data input; active LOW read gate input gap or stripe detector output serial interface data input and output serial interface enable input serial interface clock input read reference clock output digital supply voltage synchronized read data or read data output digital ground pre-amp clock output reset input; active LOW test input; connect to ground analog signal from read amplifier; positive input analog signal from read amplifier; negative input analog ground analog supply voltage extended write gate output for floppy tape drives; active LOW positive A/D reference voltage input connect external resistor differentiated signal; positive output comparator for read pulse; positive input 4
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
SYMBOL VSSA2 VDDA2 CMPB EYEB
PIN 41 42 43 44 analog ground analog supply voltage
DESCRIPTION
comparator for read pulse; negative input differentiated signal; negative output
42 VDDA2
35 VDDA1
41 VSSA2
handbook, full pagewidth
IO1 1 IO2 2 WEQEN 3 WGATE 4 VDDD1 5 CLKIN 6 CLKOUT 7 VSSD1 8 WEQCLK 9 WDIN 10 AUXBUS0/WDOUT 11
34 VSSA1
43 CMPB
40 CMPA
44 EYEB
39 EYEA
36 WGX
38 Rref
37 Vref
33 INB 32 INA 31 TEST 30 RESET 29 PACLK
SZA1000
28 VSSD2 27 SRD/RD 26 VDDD2 25 RRC 24 SCLK 23 SDEN
AUXBUS1 12
AUXBUS2 13
AUXBUS3 14
AUXBUS4 15
AUXBUS5 16
AUXBUS6 17
AUXBUS7 18
LTD 19
RG 20
GAP/STRIPE 21
SDIO 22
MGD794
Fig.2 Pin configuration.
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
FUNCTIONAL DESCRIPTION Clock oscillator and divider The clock source for the SZA1000 can be a crystal connected between pins 6 and 7, or an external clock signal connected to pin 6. This clock frequency is divided by a number programmable between 1 and 8 (see Tables 27 and 28). The resulting frequency, fs, is used as clock input to all on-chip circuits except the write equalizer. The frequency of the PACLK output signal (pin 29) is equal to fs. ADC The 8-bit ADC has a differential input. The total ADC conversion range is 1.6 V (p-p; differential). The ADC sample rate is equal to fs. High-pass filter after the ADC fs This is a first order filter with a cut-off frequency of -----------1608 It removes the DC component of the signal. Low-pass filter This low-pass filter is an even symmetrical FIR (Finite Impulse Response) filter. The number of taps depends on the sample rate reduction factor R (see Tables 30 and 31). The filter has 8 taps for R = 1 or 14 taps for R = 2 (see Table 7). The middle taps have a fixed coefficient value of +128, the coefficients of the other taps are programmable in the range -128 to +127 (see Table 6). FIR This transversal filter has 6 taps with the sample rate equal to fs (R = 1), or 11 taps with the sample rate equal to 12fs (R = 2). Tap 10 has a fixed coefficient value of +64, the coefficients of the other taps are programmable between -64 and +63 (see Table 2). The filter has 19 signal delay sections. The position of each tap can be selected from a subset of the 20 possible positions (see Tables 3 and 4). Interpolator If a sample rate of 12fs has been selected for the FIR (R = 2), it is increased once again to fs at the interpolator. Amplitude detector
SZA1000
This circuit has a separate rectifier and a positive and negative peak detector. Typical rise time (0 to 70%) for a normal MFM or 1 RLL 1,7 code input signal is --- , typical decay time fs 400 500 (100 to 30%) is programmable between --------- and --------fs fs (see Tables 10 and 11). The output is an 8-bit number that can be polled via the serial interface. In addition, the peak-to-peak value is calculated and filtered by a first order low-pass filter with a fs cut-off frequency of -----------3217 Both the filtered and unfiltered amplitudes can be read via the serial interface (see Table 44) or via the parallel output bus. Amplitude qualifier A peak is considered valid if its amplitude is above a qualification threshold. Separate qualification thresholds are used for the positive and negative peaks. Each threshold is the greater of: * a programmable level (QUAL_FIX_ POS and QUAL_FIX_NEG; control register addresses 24 and 25) * a programmable fraction (12, 38, 14, 18 or 0; see Tables 9 and 12) of the peak amplitude of the incoming signal. Gap detector When the peak-to-peak amplitude of the measured signal is below a preset limit (GAP_THRESH; control register address 28), the gap detector output is HIGH, otherwise LOW (GAP output on pin 21 must be selected; see Table 22).
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
Stripe detector This circuit is used to signal the stripes in QIC 3080, QIC 3095 and TR4 servo formats (STRIPE output on pin 21 must be selected; see Table 22). A frequency detector counts the peaks above the qualification threshold (see Table 29). An input signal containing frequencies within 25% of the programmable nominal frequency will be detected as a stripe. The microcontroller can then poll the amplitude of the following burst via the serial interface. Differentiator This function is realized by subtracting samples. The delay between samples is programmable between 1 and 6 periods of fs, split into two parts to provide a balanced delay between the differentiated and non-differentiated signals (see Tables 24 to 26). The PLL This is a fully digital PLL (Phase Lock Loop) with a programmable nominal frequency (see Tables 35 and 36), zero phase restart, programmable window shift (WIN_SHIFT; control register address 42) and a loop filter with two separate programmable settings. The PLL output reference clock is the RRC signal (pin 25; see Table 34). The frequency of this signal is rounded in time to fs. The PLL is switched to the nominal frequency if RG (pin 20) is LOW, and makes a zero phase restart at the first detected peak after RG goes HIGH. The LTD input (pin 19) is used to select between the two loop filter settings (see Tables 37 to 42). This allows for fast lock-in during preamble, before switching to a lower loop bandwidth for maximum data reliability (see Fig.3).
RRC
SZA1000
The maximum likelihood detector This detector calculates the most likely position of the peaks in the signal. It checks for (d,k) code constraints, and for alternating peaks. If an error is detected, the `most likely' correction is implemented. Separate corrections can be enabled or disabled. The SRD output of the maximum likelihood detector is valid during the rising edge of the RRC signal (see Fig.4). The maximum likelihood detector is used only to generate the SRD signal, and not to generate the time continuous RD pulse.
SRD handbook, halfpage
MGG584
Fig.4 SRD/RRC timing.
The DAC This is an internal differential 8-bit DAC operating at fs. The LPF after the DAC This analog LPF filters the time quantized signal from the DAC to retain a time continuous signal. This provides more accurate timing of the detected zero crossings in the RD pulse output. The LPF is a second order active filter with a cut-off frequency of 8 MHz.
INPUT handbook, halfpage SIGNALS RG LTD
preamble
data
The read pulse circuit A peak in the equalized signal at the interpolator output generates a read pulse. The peak is detected if a zero crossing occurs in the filtered signal after the DAC while the non-differentiated signal is above the qualification threshold.
zero phase restart PLL MODE nominal frequency fast lock-in normal read mode
MGG583
Uncommitted current sources Two uncommitted 5-bit programmable current sink DACs (0 to 2 mA) are available as IO1 and IO2 (see Table 20 for programming). These could be used, for example, to drive the tape hole detector circuit. 7
Fig.3 PLL timing diagram.
1998 Feb 16
Philips Semiconductors
Product specification
QIC digital equalizer
Parallel state bus All internal digital signals can be monitored via an 8-bit parallel bus. An external DAC or an evaluation tool such as a phase error logger for TIA (Time Interval Analyzer), drop-out and symmetry measurements can be connected to this bus for evaluation purposes (see Table 34). Write equalization This circuit has an independent clock input WEQCLK at pin 9. Write equalization can be programmed to conform to a number of formats including QIC 3010, QIC 3020, QIC 3080, QIC 3095, QIC 5010, Travan 2, Travan 3 and Travan 4. This is achieved by programming the circuit to divide a channel bit-cell into 2, 3 or 6 time slots (see Tables 13 and 14). The external WEQ clock frequency should be selected such that an integer number of between 1 and 8 clock periods fits in a time slot (see Tables 18 and 19). The width and position of the inserted write pulse can be programmed (see Tables 15 to 17). The write equalization circuit input and output signals can be independently programmed to be in either WD or WDI format (see Table 15).
SZA1000
For QIC 3010 or 3020, the recording signal is typically generated by a circuit that uses a separate crystal. An input buffer with variable delay is used to prevent errors occurring in the recorded signal. This buffer is set to its nominal position when writing begins. Signals longer than a data block can be recorded during formatting. To avoid overloading the time buffer, the circuit can resynchronize automatically during gaps in the QIC 3010 or 3020 format. Serial interface The serial interface uses 8-bit addresses and 8-bit data. Its timing is shown in Fig.5. IC mode settings, filter coefficients, scale factors and thresholds can be loaded via the serial interface. Measured signal amplitude, for example Burst level measurement at QIC 3095 or AGC control by the microcontroller, and the actual PLL frequency can be read via the serial interface. To read data from the status registers, hex address FF must be transmitted along with the required data code. The IC will then respond with the contents of the appropriate 8-bit status register (see Table 44).
1998 Feb 16
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1998 Feb 16
SDEN SCLK SDIO A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 SDEN
Philips Semiconductors
QIC digital equalizer
WRITE SETTINGS
D2
D1
D0
3-STATE
READ STATUS
9
SCLK 3-STATE
MGG585
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS AND DATA FROM MICROCONTROLLER
DATA OUT FROM DEVICE
Product specification
SZA1000
Fig.5 Serial I/O timing diagrams.
Philips Semiconductors
Product specification
QIC digital equalizer
CONTROL REGISTER Control register settings
SZA1000
The control register is accessible through the serial interface and contains 46 8-bit entries as shown in Table 1. Table 1 Control register NAME FIR_VAL0 FIR_VAL1 FIR_VAL2 FIR_VAL3 FIR_VAL4 FIR_VAL5 FIR_VAL6 FIR_VAL7 FIR_VAL8 FIR_VAL9 FIR_SEL05 FIR_SEL16 FIR_SEL27 FIR_SEL38 FIR_SEL49 FIR_SEL10 FIR_SHIFT LPF_VAL1 LPF_VAL4 LPF_VAL2 LPF_VAL5 LPF_VAL3 LPF_VAL6 LPF_SHIFT QUAL_FIX_POS QUAL_FIX_NEG QUAL_VAR_GAIN QUAL_SLOPE_DEL GAP_THRESH WEQ_SET0 WEQ_SET1 WEQ_CLK_DIV - IDAC1 IDAC2 FIR tap 1 coefficient value FIR tap 2 coefficient value FIR tap 3 coefficient value FIR tap 4 coefficient value FIR tap 5 coefficient value FIR tap 6 coefficient value FIR tap 7 coefficient value FIR tap 8 coefficient value FIR tap 9 coefficient value FIR tap positions (see Tables 3 and 4) FIR tap positions FIR tap positions FIR tap positions FIR tap positions FIR tap positions FIR output scaling (see Table 5) LPF tap coefficient value (see Table 6) LPF tap coefficient value LPF tap coefficient value LPF tap coefficient value LPF tap coefficient value LPF tap coefficient value LPF output scaling (see Table 8) Amplitude qualifier positive fixed qualification threshold Amplitude qualifier negative fixed qualification threshold Amplitude qualifier variable gain factors (see Tables 9 and 12) Amplitude detector slope qualification delay (see Table 10) Gap detector fixed threshold WEQ settings (see Tables 13 and 14) WEQ settings (see Tables 15, 16 and 17) WEQ clock divider (see Tables 18 and 19) not used IO1 DAC current (see Table 20) IO2 DAC current (see Table 20) DESCRIPTION FIR tap 0 coefficient value (see Table 2)
ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
ADDRESS 35 36 37 38 39 40 41 42 43 44 45
NAME EQ MODE0 DIFF CLK_DIV STRIPE_F EQ_MODE1 PLL_FREQL PLL_FREQH WIN_SHIFT PLL_NI PLL_NP MLD_SET
DESCRIPTION Mode setting for PACLK (pin 29) and GAP/STRIPE (pin 21) (see Tables 21, 22 and 23) differentiator settings (see Tables 24, 25 and 26) main clock divider (see Tables 27 and 28) stripe detector nominal frequency (see Table 29) equalizer mode settings PLL nominal frequency bits 0 to 7 PLL nominal frequency bits 8 to 10 PLL window shift PLL loop filter integrating gain and range PLL loop filter proportional gain maximum likelihood detector settings
Control register functions Control register functions are detailed in Tables 2 to 43. FIR FUNCTION
Addresses 0 to 9: FIR tap coefficient values
Table 2 D7 - Note 1. These are 7-bit coefficient values in two's complement notation; taps 5 to 9 are only used when R = 2; tap 10 has a fixed coefficient value of +64. Coefficient values: FIR_VAL0 to FIR_VAL9; note 1 D6 FIR_VALn.6 D5 FIR_VALn.5 D4 FIR_VALn.4 D3 FIR_VALn.3 D2 FIR_VALn.2 D1 FIR_VALn.1 D0 FIR_VALn.0
Addresses 10 to 15: FIR tap position selection
Table 3 ADDR. 10 11 12 13 14 15 Note 1. See Table 4 for the value of FSn.n. Tap position selection: FIR_SELnn; note 1 NAME FIR_SEL05 FIR_SEL16 FIR_SEL27 FIR_SEL38 FIR_SEL49 FIR_SEL10 TAPS 0 and 5 1 and 6 2 and 7 3 and 8 4 and 9 10 D7 - - - - - - D6 - - - - - - D5 FS0.2 FS1.2 FS2.2 FS3.2 FS4.2 - D4 FS0.1 FS1.1 FS2.1 FS3.1 FS4.1 - D3 FS0.0 FS1.0 FS2.0 FS3.0 FS4.0 D2 FS5.2 FS6.2 FS7.2 FS8.2 FS9.2 D1 FS5.1 FS6.1 FS7.1 FS8.1 FS9.1 D0 FS5.0 FS6.0 FS7.0 FS8.0 FS9.0
FS10.3 FS10.2 FS10.1 FS10.0
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
Table 4 Translation table: FS selection bits (FSn.n from Table 3) to tap position TAP 0,5 12 13 14 15 16 17 18 19 - - - - - - - - TAP 1,6 9 10 11 12 13 14 15 16 - - - - - - - - TAP 2,7 6 7 8 9 10 11 12 13 - - - - - - - - TAP 3,8 3 4 5 6 7 8 9 10 - - - - - - - - TAP 4,9 0 1 2 3 4 5 6 7 - - - - - - - -
SZA1000
FSn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TAP 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Address 16: FIR output scaling
Table 5 Output scaling: FIR_SHIFT FIR_SHIFT (BINARY) 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 LOW-PASS FILTER FUNCTIONS FIR OUTPUT SCALING GAIN FACTOR 1 2 4 8 16 32 64 128
Addresses 17 to 22: LPF tap coefficient values
Table 6 D7 Coefficient value: LPF_VAL1 to LPF_VAL6; notes 1 and 2 D6 D5 D4 D3 D2 D1 D0
LPF_VALn.7 LPF_VALn.6 LPF_VALn.5 LPF_VALn.4 LPF_VALn.3 LPF_VALn.2 LPF_VALn.1 LPF_VALn.0 Notes 1. These are 8-bit coefficient values in two's complement notation; taps 4 to 6 are only used when R = 2. 2. See Table 7 for the values of LPF_VALn.n
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
Table 7 LPF tap positions TAP POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 COEFFICIENT VALUES R = 1 LPF_VAL3 LPF_VAL2 LPF_VAL1 +128 +128 LPF_VAL1 LPF_VAL2 LPF_VAL3 0 0 0 0 0 0
SZA1000
COEFFICIENT VALUES R = 2 LPF_VAL6 LPF_VAL5 LPF_VAL4 LPF_VAL3 LPF_VAL2 LPF_VAL1 +128 +128 LPF_VAL1 LPF_VAL2 LPF_VAL3 LPF_VAL4 LPF_VAL5 LPF_VAL6
Address 23: LPF output scaling
Table 8 Output scaling: LPF_SHIFT LPF OUTPUT SCALING GAIN FACTOR 1 2 4 8 16 32 64 128
LPF_SHIFT (BINARY) 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 AMPLITUDE QUALIFIER/DETECTOR FUNCTIONS
Address 24: QUAL_FIX_POS and Address 25: QUAL_FIX_NEG
QUAL_FIX_POS and QUAL_FIX_NEG contain the positive and negative fixed threshold (8-bit signed) values.
Address 26: Variable gain factors
Table 9 D7 - Note 1. GP and GN set the factors of the measured amplitude that are to be used as variable qualifier thresholds: GP for the positive peaks and GN for the negative peaks. Gain factors: QUAL_VAR_GAIN; note 1 D6 - D5 GP.2 D4 GP.1 D3 GP.0 D2 GN.2 D1 GN.1 D0 GN.0
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
Address 27: Amplitude detector slope qualification delay
Table 10 Qualification delay: QUAL_SLOPE_DEL; notes 1 and 2 D7 - Notes D6 - D5 - D4 - D3 DEL.1 D2 DEL.0 D1 SL.1
SZA1000
D0 SL.0
1. DEL is the programmable compensation delay, in cycles of fs, between the qualifier and the analog zero crossing of the read pulse circuit; DEL is a 2-bit unsigned value 2. SL selects the decay time of the amplitude detectors. 500 Table 11 Amplitude detector decay time --------fs SL 0 DECAY TIME 500 --------fs 1000 -----------fs 2000 -----------fs 4000 -----------fs
Table 12 Variable qualifier threshold GP, GN 0 1 2 3 4, 5, 6, 7 VARIABLE THRESHOLD 0
1 8 1 4 3 8 1 2
1
2
3
GAP DETECTOR FUNCTIONS
Address 28: Fixed threshold: GAP_THRESH
Fixed threshold for the gap detector; 8-bit signed value. WRITE EQUALIZATION (WEQ) FUNCTIONS
Address 29: WEQ settings
Table 13 Time slots: WEQ_SET0; see Table 14 D7 - D6 - D5 - D4 - D3 - D2 N6 D1 N3 D0 N2
Table 14 Time slots in channel bit cell NUMBER OF TIME SLOTS 2 3 6 N6 0 0 1 N3 0 1 0 N2 1 0 0
1998 Feb 16
14
Philips Semiconductors
Product specification
QIC digital equalizer
Address 30: WEQ settings
Table 15 WEQ_SET1; notes 1 to 4, see also Tables 16 and 17. D7 WDI_O Notes 1. If bit WDI_O is HIGH, the circuit output is a WD signal, else a WDI signal. 2. If bit WDI_I is HIGH, the circuit expects a WD signal at the input, else a WDI signal. D6 WDI_I D5 RESYNC D4 TPS2 D3 TPS1 D2 TPS0 D1 TWS1
SZA1000
D0 TWS0
3. If the RESYNC bit is HIGH, the WEQ circuit resynchronizes its time buffer during a gap in the QIC 3010 or QIC 3020 format; this setting is only permitted if 6 time slots in a bit-cell are selected (N6 = 1; see Table 14). 4. TPS sets the position of the inserted write equalization pulse, TWS sets its width.
handbook, halfpage WD
WDI
MGG586
Fig.6 WD/WDI signal timing.
handbook, halfpage
1
0
1
1T 1 1.5 T td 1 2 T, etc. to 4 T
MGG587
0
0
1
tw 0 0 1
0
Fig.7 Position and width of write equalization pulse.
1998 Feb 16
15
Philips Semiconductors
Product specification
QIC digital equalizer
Table 16 Write equalization pulse position TPS 0 1 2 3 4 5 6 7 POSITION IN TIME SLOTS 1 2 3 4 5 6 7 8 Table 17 Write equalization pulse width TWS 0 1 2 3
SZA1000
WIDTH IN TIME SLOTS WEQ off 1 2 3
Address 31: WEQ circuit clock divider
Table 18 Division factor: WEQ_CLK_DIV; note 1 D7 - Note 1. WCD sets the division factor between WEQCLK and the frequency of the time slot. Table 19 WEQ clock division WCD 0 1 2 3 4 5 6 7 WEQ CLOCK DIVISION FACTOR 1 2 3 4 5 6 7 8 D6 - D5 - D4 - D3 - D2 WCD.2 D1 WCD.1 D0 WCD.0
UNCOMMITTED CURRENT DAC FUNCTIONS
Addresses 33 and 34: Current DACs
Table 20 DAC current: IDAC1 and IDAC2; note 1 D7 - Note IDn 1. These are 5-bit unsigned numbers; the DAC current is --------- mA. 16 D6 - D5 - D4 IDn.4 D3 IDn.3 D2 IDn.2 D1 IDn.1 D0 IDn.0
1998 Feb 16
16
Philips Semiconductors
Product specification
QIC digital equalizer
O/P SIGNAL FUNCTION: PINS 21 AND 29
SZA1000
Address 35: O/P Select pins 21 and 29
Table 21 Output signal select: EQ MODE 0; see Tables 22 and 23 D7 - D6 - D5 - D4 - D3 PA.1 D2 PA.0 D1 GAP.1 D0 GAP.0
Table 22 Output signal: pin 21 GAP 0 1 2 3 Notes 1. GAP, STRIPE or QUAL may be selected to detect gaps, stripes or valid signal peaks. All are active HIGH. 2. See also Table 34. 3. The RD output (read pulse): falling edge active. DIFFERENTIATOR FUNCTIONS OUTPUT SIGNAL ON PIN 21 GAP(1) STRIPE QUAL(2) RD(3)
Table 23 Output signal: pin 29 PA 0 1 2 3 OUTPUT SIGNAL ON PIN 29 fs - PACLK on 1 - PACLK off 0 - PACLK off 0 - PACLK off
Address 36: Differentiator settings
Table 24 DIFF; note 1 D7 - Note 1. DL1 and DL2 are programmable delays for the differentiator; DS is the gain factor of the differentiated signal. Table 25 Differentiator delay; notes 1 and 2 DLn 0 1 2 3 Notes 1. DL1 and DL2 are added to provide a maximum delay of 6 x fs cycles. 2. It is advisable to have DL1 and DL2 equal to avoid adding unwanted delay in the differentiator. DELAY IN fs CYCLES 0 1 2 3 Table 26 Differentiator gain factor DS 0 1 OUTPUT SCALING GAIN FACTOR 4 2 D6 - D5 - D4 DS D3 DL2.1 D2 DL2.0 D1 DL1.1 D0 DL1.0
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Philips Semiconductors
Product specification
QIC digital equalizer
CLOCK FUNCTIONS
SZA1000
Address 37: Main clock divider
Table 27 Clock divider: CLK_DIV; note 1 D7 - Note 1. CD selects the main clock division factor. The CLKIN frequency (pin 6) divided by this factor gives the IC's operating frequency fs (apart from the WEQ circuit). Table 28 Clock division factor CD 0 1 2 3 4 5 6 7 CLOCK DIVISION 1 2 3 4 5 6 7 8 D6 - D5 - D4 - D3 - D2 CD.2 D1 CD.1 D0 CD.0
STRIPE DETECTOR FUNCTIONS
Address 38: Stripe detector nominal frequency
Table 29 Qualification threshold: STRIPE_F; note 1 D7 - Note 1. SF is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. The nominal detection fs frequency is --------------------------------3 x ( SF + 1 ) AUXBUS, PINS 25 AND 27, SAMPLE RATE REDUCTION AND STAND-BY FUNCTIONS D6 - D5 - D4 SF.4 D3 SF.3 D2 SF.2 D1 SF.1 D0 SF.0
Address 39: Equalizer mode settings
Table 30 EQ_MODE 1; note 1, see also Tables 31 to 34 D7 - Note 1. R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches; ST selects output signal modes for pins 25 and 27. 1998 Feb 16 18 D6 STBY2 D5 ST.3 D4 ST.2 D3 ST.1 D2 ST.0 D1 STBY1 D0 R1
Philips Semiconductors
Product specification
QIC digital equalizer
Table 31 FIR/LPF Sample Rate Reduction Factor: R R1 0 1 R 2 1
SZA1000
Table 32 DAC power STBY1 0 1 D/A POWER on off
Table 33 ADC power STBY2 0 1 A/D POWER on off
Table 34 Mode settings: pins 25, 27 and AUXBUS ST 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Notes 1. QUAL is a test signal (active HIGH) used to detect valid signal peaks (see also Table 22). 2. When COMP is selected, pin 25 is switched to the output of the read pulse circuit comparator for test purposes. PLL FUNCTIONS IC MODE PLL off PLL off PLL on ADC test DAC test one shot test PLL off, AD bypass PLL off, AD bypass PLL on, AD bypass PLL on, LPF output PLL on, FIR output PLL on, PLL phase output PLL on, PLL frequency output PLL on, peak-to-peak level output PLL on, filtered level output PLL on, differentiator output PIN 27 RD RD SRD SRD RD - RD RD SRD SRD SRD SRD SRD SRD SRD SRD PIN 25 QUAL(1) COMP(2) RRC RRC COMP - QUAL COMP RRC RRC RRC RRC RRC RRC RRC RRC AUXBUS bit 0: WDOUT, bits 1 to 7 high-Z bit 0: WDOUT, bits 1 to 7 high-Z bit 0: WDOUT, bits 1 to 7 high-Z ADC output DAC output - 8-bit input to HPF 8-bit input to HPF 8-bit input to HPF LPF output after scaling FIR output after scaling and interpolator PLL phase error output PLL frequency output bits 7 to 1: LEVEL_ABS; bit 0:WDOUT bits 7 to 1: LEVEL_FIL; bit 0:WDOUT differentiator output after scaling
Addresses 40 and 41: PLL nominal frequency
Table 35 PLL_FREQL (address 40) D7 PF.7 D6 PF.6 D5 PF.5 D4 PF.4 D3 PF.3 D2 PF.2 D1 PF.1 D0 PF.0
Table 36 PLL_FREQH (address 41); note 1 D7 - Note PF 1. The nominal PLL frequency is f s x -----------2048 D6 - D5 - D4 - D3 - D2 PF.10 D1 PF.9 D0 PF.8
1998 Feb 16
19
Philips Semiconductors
Product specification
QIC digital equalizer
Address 42: Phase comparator window shift
SZA1000
WIN_SHIFT is an 8-bit number in two's complement format. The programmed phase shift is 180 x WIN_SHIFT degrees.
Address 43: PLL settings
Table 37 Address 43: PLL_NI; note 1 D7 Q1 Note 1. If LTD (pin 19) is HIGH, NI2 is selected, else NI1. Table 38 DL setting; note 1 DL SETTING DL1 = DL2 DL1 < DL2 DL1 > DL2 Note 1. The Differentiator Delay (DL) settings (see Table 25) determine the values of Q1 and Q0 that should be entered. Table 39 Integrating gain factor KI NI 0 1 2 3 KI
1 1 1 1 64
D6 Q0
D5 RNG.1
D4 RNG.0
D3 NI2.1
D2 NI2.0
D1 NI1.1
D0 NI1.0
Q1 1 1 0
Q0 1 0 1
Table 40 PLL range RNG 0 1 2 3 PLL RANGE 64 128 256 512
128 256 512
Address 44: PLL loop filter proportional gain
Table 41 PLL_NP; note 1 D7 - Note 1. If LTD (pin 19) is HIGH, NP2 is selected, else NP1. D6 - D5 NP2.2 D4 NP2.1 D3 NP2.0 D2 NP1.2 D1 NP1. 1 D0 NP1. 0
1998 Feb 16
20
Philips Semiconductors
Product specification
QIC digital equalizer
Table 42 Proportional gain factor KP NP 0 1 2 3 4 5 6 7 MAXIMUM LIKELIHOOD DETECTOR FUNCTIONS KP 1
1 1 1 1 1 2 4 8
SZA1000
16 32
- -
Address 45: Settings
Table 43 Address 45: MLD_SET D7 en_k(1) Notes 1. Check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. For MFM code: k = 3 (ks = 4), for RLL(1,7) code: k = 7 (ks = 8). 2. Check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between two bit cells with transitions. d = 1 for both MFM and RLL(1,7) codes 3. Check partial response constraints; delete incorrect peaks. 4. Check partial response constraints; add missing peaks. 5. ks = k + 1. STATUS REGISTER The status register contains 5 status bytes. The contents of the status bytes can be read via the serial interface. Table 44 Status bytes; notes 1 to 4 ADDRESS 255 255 255 255 255 Notes 1. The levels are measured behind the re-sampling block (interpolator) (see Fig.1). FREQ 2. Actual PLL frequency is an 8-bit unsigned number: f s x ----------------256 3. LEVEL_FIL can be used for reading of the burst levels, or in an AGC loop (with the TZA1000 preamplifier). 4. LEVEL_POS, LEVEL_NEG, LEVEL_ABS and LEVEL_FIL are 8-bit numbers in two's complement format. 1998 Feb 16 21 DATA 0 1 2 3 4 NAME FREQ LEVEL_POS LEVEL_NEG LEVEL_ABS LEVEL_FIL DESCRIPTION actual frequency of PLL positive peaks in measured level negative peaks in measured level measured peak-to-peak level low-pass filtered LEVEL_ABS D6 en_d(2) D5 PR1(3) D4 PR0(4) D3 ks3(5) D2 ks2(5) D1 ks1(5) D0 ks0(5)
Philips Semiconductors
Product specification
QIC digital equalizer
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD1 VDDD2 VDDA1 VDDA2 Vi II II(n) Ptot Tamb Tj Tstg VES(HB) VES(MM) Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistance. PARAMETER digital supply voltage digital supply voltage analog supply voltage analog supply voltage input voltage input current on supply pins input current on remaining pins maximum total power dissipation ambient temperature junction temperature storage temperature electrostatic handling: human body model electrostatic handling: machine model note 1 note 2 CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3 -0.3 -50 -10 - -30 -30 -50 -3000 -300
SZA1000
MAX. +5.5 +5.5 +5.5 +5.5 +50 +10 +1100 +85 +125 +150 +3000 +300 V V V V
UNIT
VDD + 0.3 V mA mA mW C C C V V
2. Equivalent to discharging a 200 pF capacitor through a 25 series resistance and a 2.5 H series inductance. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 70 UNIT K/W
QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E".
1998 Feb 16
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Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
CHARACTERISTICS VDDD1 = VDDD2 = VDDA1 = VDDA2 = 5 V 5%; fs = fclk(CLKIN) = 24 MHz; Vref = 2 V 5%; Rref = 10 k, unless otherwise specified. SYMBOL VDDD1 VDDD2 VDDA1 VDDA2 IDDD1; IDDD2 IDDA1; IDDA2 PARAMETER digital supply voltage digital supply voltage analog supply voltage analog supply voltage digital supply current analog supply current r = 2, no WEQ STBY1 = 0; STBY2 = 1; see Table 30 STBY 1= 1; STBY2 = 0 fclk(CLKIN) fclk(WEQCLK) read circuit clock frequency WEQ circuit clock frequency N6 = 0; see Table 14; (3080; 3095) CONDITIONS 4.5 4.5 4.5 4.5 - - MIN. TYP. 5.0 5.0 5.0 5.0 32 50 5.5 5.5 5.5 5.5 80 65 MAX. UNIT V V V V mA mA
- - -
26 24 -
35 24 36
mA MHz MHz
VIL VIH VOL VOH Ci Analog section Vref Iref Vcnv(A/D) VCM(A/D) Ri(A/D) Ci(A/D) II(32) II(33) V38 IO(1)
LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage input capacitance Io = -4 mA Io = +4 mA I/O pins high-Z; note 1
- 0.7VDD - VDD - 0.5 -
- - - - -
0.3VDD - 0.5 - 5
V V V V pF
reference voltage (pin 37) reference current (pin 37) A/D conversion range A/D common mode voltage A/D input resistance A/D input capacitance DC input current (INA) DC input current (INB) voltage on pin 38 (Rref) output current on pin 1 (IO1) IDAC1 = 0; see Table 20 IDAC1 = 31 output current on pin 2 (IO2) IDAC2 = 0; see Table 20 IDAC2 = 31 D/A differential output range (peak-to-peak) D/A common mode voltage note 2 note 2
1.8 1.0 - 2 2.3 - - - - - 1.40 - 1.40 1.5 1.0
2.0 1.7 1.6 2.5 3.3 3 0.42 0.13 2.0 0.0 1.95 0.0 1.95 1.72 1.16
2.2 2.1 - 3 4.4 5 0.6 0.2 - 0.05 2.60 0.05 2.60 1.8 1.4
V mA V V k pF mA mA V mA mA mA mA V V
IO(2)
Vo(dif) VCM(D/A)
1998 Feb 16
23
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
SYMBOL f-3dB(cutoff)(LPF) VCM(COMP) Ri(COMP) VIO(COMP) Serial interface fclk(SIO) tsu(D-CLK) th(D-CLK) td(1) td(2) tsu(EN-CLK) th(EN-CLK) tCLKINH tCLKINL tRDL tsu(SRD-RRC) th(SRD-RRC) tRRCL tsu(AUX-CLKIN) th(AUX-CLKIN) tPACLKH tPACLKL td(AUX-PACLK) td(PACLK-AUX)
PARAMETER -3dB cut-off frequency, analog LPF (DAC filter) comparator common mode voltage comparator input resistance comparator offset voltage
CONDITIONS note 2 note 3 note 4 note 4 - 1.0 17 - - 10 note 5
MIN.
TYP. 8 1.16 26 - - - - - - - - - - - - - - - - - 1.4 35 45
1
MAX.
UNIT MHz V k mV
serial i/f clock set-up time: data-to-clock hold time: data-to-clock delay clock: new data delay clock: old data set-up time: enable-to-clock hold time: enable-to-clock
4fs
MHz ns ns ns ns ns ns
- - 2ts + 10 - - - - - 2ts + 10
ts + 10 - ts ts + 10 ts + 10 15 15 ts
Digital read section CLKIN HIGH time CLKIN LOW time RD LOW time set-up time: SRD-to-RRC hold time: SRD-to-RRC RRC LOW time input set-up time: AUXBUS-to-CLKIN (pin 6) input hold time: AUXBUS-to-CLKIN (pin 6) PACLK HIGH time PACLK LOW time delay: AUXBUS-to-PACLK (pin 29) delay: PACLK to AUXBUS note 7 note 7 note 8 notes 7 and 8 note 6 note 6 note 6 ns ns ns
tCLKINL - 5 - 0.2Co(L)(SRD) tCLKINH - 2 - 0.2Co(L)(RRC) tCLKINL - 5 - 0.2Co(L)(RRC) - -
tCLKINL + 2 ns - 0.2Co(L)(RRC) - tCLKINL - - tCLKINH tCLKINL 10 + 0.2Co(L)(AUX) ns ns ns ns ns ns ns
tCLKINH - 2 - - 0.2Co(L)(PACLK) tCLKINL - 5 - - 0.2Co(L)(PACLK) - - - -
5+ ns 0.2Co(L)(PACLK)
1998 Feb 16
24
Philips Semiconductors
Product specification
QIC digital equalizer
SZA1000
SYMBOL
PARAMETER
CONDITIONS N2 = 1 or N3 = 1; - see Table 14 N6 =1; see Table 14 - 10 10 N2 = 1 or N3 = 1; 5 see Table 14 N2 = 1 or N3 = 1; 10 see Table 14 WDI_I = 0; see Table 15 note 9 N6 = 1; see Table 14 10
MIN.
TYP. - 24 - - - - - - -
MAX.
UNIT
Write equalization section fclk(WEQ) WEQ clock frequency 36 24 - - - - - tWEQH - MHz MHz ns ns ns ns ns ns %
tWEQL tWEQH tsu(WD-WEQCLK) th(WD-WEQCLK) tIL(WDIN) tOL(WDOUT)
WEQ LOW time WEQ HIGH time setup time: WDIN-to-WEQCLK hold time: WD-to-WEQCLK WDIN input LOW time (WDI mode) WDOUT output LOW time (WDI mode)
tWEQH - 2-0.2x Co(L)(WDOUT) 0.5
fo(WDIN-WEQCLK) frequency offset WDIN-WEQCLK Notes 1. Pins 3, 4, 6, 9 to 20, 22, 23, 24, 30 and 31.
2. Measured at pins 39 and 44 with a 10 M/15 pF load. 3. Measured at pins 40 and 43. 4. Differential pins 40 and 43. 5. 1 t s = --fs
6. Co(L)(SRD) is the external load (pF), at SRD (pin 27) for Co(L)(SRD) < 50 pF. Co(L)(RRC) is the external load (pF), at RRC (pin 25) for Co(L)(RRC) < 50 pF. 7. Co(L)(PACLK) is the external load (pF), at PACLK (pin 29) for Co(L)(PACLK) < 50 pF. 8. Co(L)(AUX) is the external load (pF), at AUX0 to AUX7 (pins 11 to 18) for Co(L)(AUX) < 50 pF. 9. Co(L)(WDOUT) is the external load (pF), at WDOUT (pin 11) for Co(L)(WDOUT) < 50 pF.
1998 Feb 16
25
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Feb 16 26
th(EN-CLK) SDEN SCLK 3-STATE
MGG656
TIMING DIAGRAMS
Philips Semiconductors
Serial interface
ull pagewidth
QIC digital equalizer
tsu(EN-CLK) th(EN-CLK) SDEN tsu(D-CLK) th(D-CLK)
WRITE SETTINGS th(EN-CLK)
tsu(EN-CLK)
SCLK 3-STATE
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tsu(EN-CLK) tsu(D-CLK) th(D-CLK)
READ STATUS th(EN-CLK)
tsu(EN-CLK)
td(1)
td(2)
SDIO
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS AND DATA FROM MICROCONTROLLER
DATA OUT FROM DEVICE
Product specification
SZA1000
Fig.8 Serial I/O showing set-up, hold and delay timing.
Philips Semiconductors
Product specification
QIC digital equalizer
Digital read section
SZA1000
handbook, full pagewidth
tsu(SRD-RRC) th(SRD-RRC)
SRD
RRC tsu(AUX-CLKIN) th(AUX-CLKIN)
tCLKINL CLKIN AUX0 to 7 INPUT
tCLKINH
tPACLKL PACLK
tPACLKH
td(PACLK-AUX)
td(AUX-PACLK)
AUX0 to 7 OUTPUT
MGG657
Fig.9 Digital read section showing set-up, hold and delay timing.
Write equalization section
handbook, full pagewidth
tWEQH tWEQL WEQCLK) th(WD-WEQCLK) WDIN (WDI mode) tsu(WD-WEQCLK) tIL(WDIN)
WDIN (WD mode) tOL(WDOUT) WDOUT (WDI mode)
MGG658
Fig.10 WEQ section showing set-up and hold timing.
1998 Feb 16
27
Philips Semiconductors
Product specification
QIC digital equalizer
PACKAGE OUTLINE
SZA1000
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Feb 16
28
Philips Semiconductors
Product specification
QIC digital equalizer
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
SZA1000
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Feb 16
29
Philips Semiconductors
Product specification
QIC digital equalizer
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SZA1000
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Feb 16
30
Philips Semiconductors
Product specification
QIC digital equalizer
NOTES
SZA1000
1998 Feb 16
31
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/00/01/pp32
Date of release: 1998 Feb 16
Document order number:
9397 750 01122

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